The present disclosure herein relates to a processor, and more particularly, to a multi-core processor including a plurality of processors and a cache management method therefor.
Central processing units (CPUs) are widely applied in the field of system semiconductors. A processor may read a program from a main memory to perform a calculation according to a procedure. Furthermore, the processor may store a calculation result (i.e., processing result) in the main memory. A cache may be disposed between the processor and the main memory to improve the performance and speed of data exchange between the processor and the main memory. A processing result of the processor or a portion of a program stored in the main memory may be stored in the cache. The cache has higher read/write speeds in comparison with the main memory exemplified by a dynamic random access memory (DRAM). In addition, in the case where the cache is used between the processor and the main memory, an operation fault of the processor may be monitored or a monitored fault may be corrected.
Recently, a multi-core technology and a cache memory have become more important for providing high performance and high reliability required for systems. Furthermore, a multi-core technology and a technology for providing cache coherence are being actively applied to various mobile devices to satisfy the requirement of high performance A technology for recognizing and recovering from a fault of a CPU is necessarily required for a multi-core CPU from which high performance and high reliability are required.